| View Larger Image | Design for Manufacturability and Yield for Nano-Scale CMOS (Integrated Circuits and Systems) | Hardcoverby Charles Chiang (Author), Jamil Kawa (Author)
| List Price: | $135.00 | | | Available: | Usually ships in 24 hours |
| | Binding: | Hardcover | | Publisher: | Springer | | Edition: | 1st Edition | | Page Count: | 254 Pages | | Publication Date: | August 24, 2007 | | Sales Rank: | 359,371th |
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ACCESSORIES |
| SystemVerilog for Verification: A Guide to Learning the Testbench Language Features
by Chris Spear (Author)
SystemVerilog for Verification teaches the reader how to use the power of the new SystemVerilog testbench constructs plus methodology without requiring in-depth knowledge of Object Oriented Programming or Constrained Random Testing. The book covers the SystemVerilog verification constructs such as classes, program blocks, C interface, randomization, and functional coverage. SystemVerilog for Verification also reviews some design topics such as interfaces and array types. There are extensive...
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| SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling
by Stuart Sutherland (Author), Simon Davidmann (Author), Peter Flake (Author), P. Moorby (Foreword)
SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs. The first edition of this book addressed the first aspect of the SystemVerilog extensions to Verilog. Important modeling features were...
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| Data Converters
by Franco Maloberti (Author)
This book is the first graduate-level textbook presenting a comprehensive treatment of Data Converters. The advancement of digital electronics urged the availability of a still missing support for teaching and self-learning analog-digital interfaces at many levels: the specification, the conversion methods and architectures, the circuit design and the testing. This book, after the necessary study of the background theoretical elements, covers aspects and provides elements for a deep and...
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EDITORIAL REVIEWS |
Product Description
As we approach the 32 nm CMOS technology node the design and manufacturing communities are dealing with a lithography system that has to print circuit artifacts that are significantly less than half the wavelength of the light source used, with new materials, with tighter pitches, and higher aspect ratio metallurgies. This reality has resulted in three main manufacturability issues that have to be addressed: printability, planarization, and intra-die variability. Addressing in depth the fundamentals impacting those three issues at all the stages of the design process is not a luxury one can ignore. Manufacturability and yield are now one and the same and are no longer a fabrication, packaging, and test concerns; they are the concern of the whole IC community. Yield and manufacturability have to be designed in, and they are everybody's responsibility. Design for Manufacturability and Yield for Nano-Scale CMOS walks the reader through all the aspects of manufacturability and yield in a nano-CMOS process and how to address each aspect at the proper design step starting with the design and layout of standard cells and how to yield-grade libraries for critical area and lithography artifacts through place and route, CMP model based simulation and dummy-fill insertion, mask planning, simulation and manufacturing, and through statistical design and statistical timing closure of the design. It alerts the designer to the pitfalls to watch for and to the good practices that can enhance a design's manufacturability and yield. This book is a must read book the serious practicing IC designer and an excellent primer for any graduate student intent on having a career in IC design or in EDA tool development. |
CUSTOMER REVIEWS (Average Customer Rating: 4.0 based on 1 review)
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Design for Yield by Paolo Pezzati (France)  4 Stars
December 16, 2007
Design for Manufacturability and Yield for Nano-Scale CMOS (Series on Integrated Circuits and Systems)
This book provides a good overview of the challenges in IC design for manufacturing and yield optimization.
It covers all the advanced problems at 65nm and below such as random and systematic variability, CMP and statistical design analysis.
The book represents an useful introduction to those topics for students, engineers and technical managers in the microelectronics industry.
The drawbacks are:
- very poor graphical quality of pictures and diagrams
- lack of an index
- some missing of relevant industrial examples (devices, metrics, analysis results)
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SIMILAR PRODUCTS |
| Design for Manufacturability and Statistical Design: A Constructive Approach (Integrated Circuits and Systems)
by Michael Orshansky (Author), Sani R. Nassif (Author), Duane Boning (Author)
This book will present a comprehensive overview of methods that need to be mastered in understanding state-of-the-art design for manufacturability and statistical design methodologies. Broadly, design for manufacturability is a set of techniques that attempt to fix the systematic sources of variability, such as those due to photolithography and CMP. Statistical design, on the other hand, deals with the random sources of variability. Both paradigms operate within a common framework, and their...
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| Static Timing Analysis for Nanometer Designs: A Practical Approach
by J. Bhasker (Author), Rakesh Chadha (Author)
The book covers topics such as cell timing and power modeling; interconnect modeling and analysis, delay calculation, crosstalk, noise and the chip timing verification using static timing analysis. For each of these topics, the book provides a theoretical background as well as detailed examples to elaborate the concepts. The static timing analysis topics covered start from verification of simple blocks useful for a beginner to this field. The topics then extend to complex nanometer designs with...
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| Fabless Semiconductor Implementation
by Rakesh Kumar (Author)
Discover How to Launch and Succeed as a Fabless Semiconductor Firm Fabless Semiconductor Implementation takes you step-by-step through the challenges faced by fabless firms in the development of integrated circuits. This expert guide examines the potential pitfalls of IC implementation in the rapidly growing fabless segment of the semiconductor industry and elaborates how to overcome these difficulties. It provides a comprehensive overview of the issues that executives and...
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| System-on-Chip Test Architectures: Nanometer Design for Testability (Systems on Silicon)
by Laung-Terng Wang (Author), Charles E. Stroud (Author), Nur A. Touba (Author)
Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost.
This book is a comprehensive guide to new VLSI Testing and Design-for-Testability...
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| Leakage in Nanometer CMOS Technologies (Integrated Circuits and Systems)
by Siva G. Narendra (Editor), Anantha Chandrakasan (Editor)
The goal of Leakage in Nanometer CMOS Technologies is to provide ample detail so that the reader can understand why leakage power components are becoming increasingly relevant in CMOS systems that use nanometer scale MOS devices. Leakage current sources at the MOS device level including sub-threshold and different types of tunneling are discussed in detail. The book covers promising solutions at the device, circuit, and architecture levels of abstraction. Manifestation of these MOS device...
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