| View Larger Image | Closing the Gap Between ASIC & Custom: Tools and Techniques for High-Performance ASIC Design | Hardcoverby David Chinnery (Author), Kurt Keutzer (Author)
| List Price: | $159.00 | | Price: | $142.34 | | You Save: | $16.66 (10%) | | | Available: | Usually ships in 24 hours |
| | Binding: | Hardcover | | Publisher: | Springer | | Edition: | 1st Edition | | Page Count: | 432 Pages | | Publication Date: | June 30, 2002 | | Sales Rank: | 843,570rd |
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ACCESSORIES |
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Rapid Prototyping of Digital Systems: Quartus II Edition provides an exciting and challenging laboratory component for undergraduate digital logic and computer design courses using FPGAs and CAD tools for simulation and hardware implementation. The more advanced topics and exercises also make this text useful for upper level courses in digital logic, programmable logic, and embedded systems. This new version of the widely used Rapid Prototyping of Digital Systems, Second Edition, now uses...
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| Algorithms for VLSI Physical Design Automation, Third Edition
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Algorithms for VLSI Physical Design Automation, Third Edition covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concepts and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in...
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| Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime®
by Himanshu Bhatnagar (Author)
Advanced ASIC Chip Synthesis: Using Synopsys TM Design CompilerTM Physical CompilerTM and PrimeTime TM, Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail. The emphasis of this book is on real-time application of...
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EDITORIAL REVIEWS |
Product Description
Carefully details design tools and techniques for high-performance ASIC design techniques. These techniques are illustrated by designs running two to three times the speed of typical designs in the same process generation. |
CUSTOMER REVIEWS (Average Customer Rating: 5.0 based on 2 reviews)
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Shows the way. by J. W. Byrn (Fort Collins, CO USA)  5 Stars
January 09, 2007
This is a very useful book to help focus on how to develop high performance designs. It is a little dated on the technologies covered but gets the job done. One thing to remember is that microprocessor development methods usually will become ASIC development methods after a number of years and related EDA tool development.
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A study of fast processor design by Jonah Probell (Silicon Valley & Boston) 5 Stars
February 09, 2004
Whether trying to maximize the speed of a standard cell ASIC processor design or minimize the design time of a full custom processor this book describes, in detail, the considerations involved. The authors draw on real-world designs and extensively review several in particular. The book describes the impact on resulting processor performance of pipeline depth, clock tree design, register and latch choice, setup and clock-to-q times, slack passing, dynamic logic, logic design style, richness of standard cell library, wire and transistor sizing, floorplanning and other layout concerns, and the exploitation of process variation.This book focuses strictly on processor circuit design and does not discuss software design, instruction set architecture, or die size and power issues.
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SIMILAR PRODUCTS |
| Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low Power Design
by David Chinnery (Author), Kurt Keutzer (Author)
This book carefully details design tools and techniques for realizing low power and energy efficiency in a highly productive design methodology. Important topics include:- Microarchitectural techniques to reduce energy per operation- Power reduction with timing slack from pipelining- Analysis of the benefits of using multiple supply and threshold voltages- Placement techniques for multiple supply voltages- Verification for multiple voltage domains- Improved algorithms for gate sizing, and...
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| Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime®
by Himanshu Bhatnagar (Author)
Advanced ASIC Chip Synthesis: Using Synopsys TM Design CompilerTM Physical CompilerTM and PrimeTime TM, Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail. The emphasis of this book is on real-time application of...
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Low-Energy FPGAs: Architecture and Design is a primary resource for both researchers and practicing engineers in the field of digital circuit design. The book addresses the energy consumption of Field-Programmable Gate Arrays (FPGAs). FPGAs are becoming popular as embedded components in computing platforms. The programmability of the FPGA can be used to customize implementations of functions on an application basis. This leads to performance gains, and enables reuse of expensive...
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| Low Power Methodology Manual: For System-on-Chip Design (Integrated Circuits and Systems)
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“Tools alone aren't enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to describe [such] [a] low-power methodology with a practical, step-by-step approach.” Richard Goering, Software Editor, EE Times “Excellent compendium of low-power techniques and...
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| Leakage in Nanometer CMOS Technologies (Integrated Circuits and Systems)
by Siva G. Narendra (Editor), Anantha Chandrakasan (Editor)
The goal of Leakage in Nanometer CMOS Technologies is to provide ample detail so that the reader can understand why leakage power components are becoming increasingly relevant in CMOS systems that use nanometer scale MOS devices. Leakage current sources at the MOS device level including sub-threshold and different types of tunneling are discussed in detail. The book covers promising solutions at the device, circuit, and architecture levels of abstraction. Manifestation of these MOS device...
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