| View Larger Image | On-Chip Networks (Synthesis Lectures on Computer Architecture) | Paperbackby Li-Shiuan Peh (Author), Natalie Enright Jerger (Author)
| List Price: | $40.00 | | Price: | $34.20 | | You Save: | $5.80 (14%) | | | Available: | Usually ships in 24 hours |
| | Binding: | Paperback | | Publisher: | Morgan and Claypool Publishers | | Edition: | 1st Edition | | Page Count: | 142 Pages | | Publication Date: | July 24, 2009 | | Sales Rank: | 1,093,371st |
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Product Description
With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High bandwidth and low latency within the on-chip network must be achieved while fitting within tight area and power budgets. In this lecture, we examine various fundamental aspects of on-chip network design and provide the reader with an overview of the current state-of-the-art research in this field. Table of Contents: Introduction / Interface with System Architecture / Topology / Routing / Flow Control / Router Microarchitecture / Conclusions |
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