Buried silver nanoparticles improve organic transistors

August 10, 2010

College Park, MD (August 10, 2010) -- Out of sight is not out of mind for a group of Hong Kong researchers who have demonstrated that burying a layer of silver nanoparticles improves the performance of their organic electronic devices without requiring complex processing. Their findings in a report published in the journal Applied Physics Letters, which is published by the American Institute of Physics (AIP).

A team led by Professors Paddy Chan and Dennis Leung of the Hong Kong Polytechnic University has shown that a simple layer of silver nanoparticles placed between two layers of the organic semiconductor pentacene improves performance just as much as painstakingly placing nanoparticles atop a tiny floating gate region.

Because certain metal nanoparticles trap electric charges very effectively, they are becoming a popular additive for enhancing transistor performance and producing thinner transistors. Sandwiching a layer of nanoparticles is much more compatible with the low-cost, continuous roll-to-roll fabrication techniques used to make organic electronics than the more intricate patterning required to put material just in the transistor gate area.

Moreover, Chan's group showed that the thickness of the nanoparticle layer changes the device performance in predictable ways that can be used to optimize transistor performance to meet application requirements.

Transistors made with a 1-nanometer nanoparticle layer, for example, have stable memory that lasts only about three hours, which would be suitable for memory buffers. Transistors having a 5-nanometer-thick layer are more conventional and retain their charge for a much longer time.

"We believe that organic memory has a very high potential for use in next-generation memory devices -- such as touchscreens and electronic paper -- where their flexibility and low-cost are most important," said Dr. Sumei Wang, a postdoctoral research fellow of the team.
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The article, "Nonvolatile organic transistor-memory devices using various thicknesses of silver nanoparticle layers" by Paddy K. L. Chan, Sumei Wang and Chi Wah Leung will appear in the journal Applied Physics Letters. See: http://apl.aip.org/applab/v97/i2/p023511_s1

Journalists may request a free PDF of this article by contacting jbardi@aip.org

This work was supported by research grants from Hong Kong Polytechnic University and through funding from HKSAR (Hong Kong Special Administrative Region) through UGC (University Grants Committee).

ABOUT APPLIED PHYSICS LETTERS

Applied Physics Letters, published by the American Institute of Physics, features concise, up-to-date reports on significant new findings in applied physics. Emphasizing rapid dissemination of key data and new physical insights, Applied Physics Letters offers prompt publication of new experimental and theoretical papers bearing on applications of physics phenomena to all branches of science, engineering, and modern technology. Content is published online daily, collected into weekly online and printed issues (52 issues per year). See: http://apl.aip.org/

ABOUT AIP

The American Institute of Physics is a federation of 10 physical science societies representing more than 135,000 scientists, engineers, and educators and is one of the world's largest publishers of scientific information in the physical sciences. Offering partnership solutions for scientific societies and for similar organizations in science and engineering, AIP is a leader in the field of electronic publishing of scholarly journals. AIP publishes 12 journals (some of which are the most highly cited in their respective fields), two magazines, including its flagship publication Physics Today; and the AIP Conference Proceedings series. Its online publishing platform Scitation hosts nearly two million articles from more than 185 scholarly journals and other publications of 28 learned society publishers.

American Institute of Physics

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