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Seeing the next dimension of computer chips

October 10, 2017

Osaka - A research collaboration between Osaka University and the Nara Institute of Science and Technology for the first time used scanning tunneling microscopy (STM) to create images of atomically flat side-surfaces of 3D silicon crystals. This work helps semiconductor manufacturers continue to innovate while producing smaller, faster, and more energy-efficient computer chips for computers and smartphones.

Our computers and smartphones each are loaded with millions of tiny transistors. The processing speed of these devices has increased dramatically over time as the number of transistors that can fit on a single computer chip continues to increase. Based on Moore's Law, the number of transistors per chip will double about every 2 years, and in this area it seems to be holding up. To keep up this pace of rapid innovation, computer manufacturers are continually on the lookout for new methods to make each transistor ever smaller.

Current microprocessors are made by adding patterns of circuits to flat silicon wafers. A novel way to cram more transistors in the same space is to fabricate 3D-structures. Fin-type field effect transistors (FETs) are named as such because they have fin-like silicon structures that extend into the air, off the surface of the chip. However, this new method requires a silicon crystal with a perfectly flat top and side-surfaces, instead of just the top surface, as with current devices. Designing the next generation of chips will require new knowledge of the atomic structures of the side-surfaces.

Now, researchers at Osaka University and the Nara Institute of Science and Technology report that they have used STM to image the side-surface of a silicon crystal for the first time. STM is a powerful technique that allows the locations of the individual silicon atoms to be seen. By passing a sharp tip very close to the sample, electrons can jump across the gap and create an electrical current. The microscope monitored this current, and determined the location of the atoms in the sample.

"Our study is a big first step toward the atomically resolved evaluation of transistors designed to have 3D-shapes," study coauthor Azusa Hattori says.

To make the side-surfaces as smooth as possible, the researchers first treated the crystals with a process called reactive ion etching. Coauthor Hidekazu Tanaka says, "Our ability to directly look at the side-surfaces using STM proves that we can make artificial 3D structures with near-perfect atomic surface ordering."
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Osaka University

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