New transistor could keep computer evolution on track

December 07, 2000

WEST LAFAYETTE, Ind. -- Purdue University engineers have new information contradicting the most dire predictions about the imminent demise of Moore's Law, a general rule that is central to the evolution and success of the computer industry.

The rule states that the number of transistors on a computer chip doubles about every 18 months, driving rapid progress in computers and telecommunications. Doubling the number of devices that can fit on a computer chip translates into a similar increase in performance.

Because this doubling requires circuits to be made smaller and smaller, it is thought the limits of physics will soon make it impossible to continue at the same pace, or that it eventually will become too expensive to shrink circuits any more, hindering further progress. Some observers have predicted Moore's Law will hit a brick wall in about a decade.

However, a new simulation tool has shown that an innovative type of transistor could keep Moore's Law in force until 2025, or beyond. This would give scientists breathing room to develop entirely new technologies to replace integrated circuits made from silicon.

The simulation tool was developed by a research team led by Mark Lundstrom and Supriyo Datta, professors of electrical and computer engineering at Purdue. Also included on the team are DeJan Jovanovic, a computational scientist at Motorola Inc., and Professor Jerry Fossum, an expert on advanced silicon transistors at the University of Florida.

Graduate student Zhibin Ren will discuss the research findings on Wednesday (12/13), during the International Electron Devices Meeting, sponsored by the Institute of Electrical and Electronics Engineers, in San Francisco.

The simulation tool tested the performance of an experimental transistor, called a double-gate transistor, which carries twice the electrical current and could work more than twice as fast as conventional devices. Lundstrom has demonstrated that double-gate transistors one-tenth the length of the best conventional transistors could perform as well as current devices. Critical components in the transistors, electrodes known as gates, are only 10 nanometers long, compared to 100 nanometers for conventional transistors. To put those dimensions into perspective, a human red blood cell is about 7,500 nanometers across, and one nanometer is roughly 10 atoms wide.

Researchers are concerned that, as transistors are shrunk below 100 nanometers, it will be difficult to maintain high performance and fabrication quality.

The major problem is that conventional silicon transistors, the on-off switches that make solid-state electronics possible, will cease to function below a certain thickness. That's because at such thin dimensions quantum mechanics -- in which electrons behave as both waves and particles -- begin to have a measurable effect on performance. Essentially, the ultra-thin layer of insulating material in such small transistors will fail to stop electrons from flowing, and the transistor will no longer function as a switch.

However, that problem could be solved by double-gate transistors, Lundstrom said.

The new simulation tool evaluates transistor performance with a sophisticated technique earlier used by Datta to simulate electrical conduction in individual molecules. When applied to transistors, the same method predicts that a double-gate transistor can continue to perform well at gate lengths as short as 10 nanometers, and perhaps even shorter, Lundstrom said.

"That means, if we could learn how to manufacture a device like this, we could extend Moore's Law to the year 2025," he said. Researchers at Purdue, the University of California at Berkeley and the IBM Watson Research Center have already demonstrated working double-gate transistors.

During the San Francisco conference, Lundstrom will announce that the simulation tool, called nanoMOS, is now available to any researcher who wants to use it. Engineers at Purdue will make the tool available through an unusual system called the Purdue Nanotechnology Simulation Hub, or nanoHub.

There is no need to download the simulation software or learn new operating codes because the nanoHub uses a network-computing platform that automatically enables computer users to run programs with conventional Web browsers. They simply acquire an account and begin using the software.

Purdue researchers say they know of only two other teams in the world who have created similar "full quantum" simulation tools. But those tools were developed in the private sector and are not accessible to the research community at large.

"We want to accelerate progress in nanoelectronics by making this tool available to everyone," Lundstrom said.

The nanoHub can be accessed at

Writer: Emil Venere, (765) 494-4709,

Related Web sites: nanoHub:
Mark Lundstrom:
Supriyo Datta:

Purdue University
News Service
1132 Engineering Administration Building
West Lafayette, IN 47907-1132
Voice: 765-494-2096
FAX: 765-494-0401

NOTE TO JOURNALISTS: An electronic copy of the research paper discussed in this news release is available from Emil Venere, (765) 494-4709,

Sources: Mark Lundstrom, (765) 494-3515, Supriyo Datta, (765) 494-3511,

The Ballistic Nanotransistor: A Simulation Study
Zhibin Ren, Ramesh Venugopal, Supriyo Datta and Mark Lundstrom
Purdue University, West Lafayette, IN
Dejan Jovanovic, Motorola/LANL, Los Alamos
Jerry Fossum, University of Florida, Gainesville, FL

The device design and physics issues of ballistic double-gate (DG) MOSFETs are explored using semiclassical and quantum simulations. We find that tunneling from source-to-drain increases the off-current but decreases the on-current for an L=10 nm model transistor. We also show that source-to-drain tunneling sets a scaling limit at less than about L=10 nm, but to achieve this limit, ultra-thin bodies are necessary to control classical two-dimensional short-channel effects. Finally, we show that to meet performance targets at low voltages, near ballistic performance is necessary, and we estimate the mobility that will be required for these ultra-thin silicon films.

Purdue University

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