As Moore’s Law gradually slows down, improvements in integrated circuit performance no longer rely solely on the miniaturization of transistors. Recently, a study published in Journal of Functional Materials and Devices proposed a new “time-scaling” methodology that reexamines the performance evolution from devices to systems by treating the time constant τ as a unified optimization objective.
The research team applied this concept to superconducting single-flux-quantum (SFQ) circuits. Although these circuits feature picosecond-scale switching time and extremely low power consumption, their large-scale integration remains constrained by issues such as planar layout, routing congestion, and clock skew. Unlike the “logic folding” approach in the semiconductor field, which relies on package-level 3D integration, the dual-active-layer structure proposed in this study directly constructs two layers of Josephson junction active devices within a single-chip cryogenic process stack, achieving true gate-level 3D integration.
The researchers developed a τ-decomposition model for SFQ circuits, breaking down time delays into multiple independently optimizable components, including device switching, interlayer uniformity, logic cell delays, lateral and vertical interconnect delays, and clock distribution. Based on this model, they validated the effectiveness of the dual-active-layer approach in test circuits such as ISCAS-c17, a 4-bit Kogge-Stone adder, and a shift register. The results show that, for sufficiently large circuits, the dual-active-layer approach can achieve a net timing compression of up to 28.8%.
The study also notes that the dual-active-layer approach is not suitable for all scenarios. When circuit sizes are too small, the additional delay introduced by vertical vias may outweigh the savings from planar routing. Furthermore, more active layers do not necessarily yield better results; the marginal benefit of a three-layer structure compared to a two-layer one decreases significantly, and timing violations may even occur. Consequently, the team calls for the development of “time-aware” (τ-aware) electronic design automation tools to help designers make trade-offs centered on time compression during layer allocation, 3D layout, and timing analysis.
This research provides a new theoretical framework and engineering path for the development of superconducting integrated circuits in the post-Moore’s Law era, emphasizing that future advances in computing systems should focus on “shorter time paths” rather than “more devices.”
Time scaling methodology for superconducting dual-active-layer integrated circuits
30-Jun-2026