□ A research team led by Professor Jae Eun Jang and Dr. Goeun Pyo from the Department of Electrical Engineering and Computer Science at DGIST (President Kunwoo Lee) has developed, for the first time in the world, “dual-modulated vertically stacked transistors” that operate stably without current leakage even in two-dimensional nanoscale channel structures.
□ In recent years, the semiconductor industry has faced physical limitations as the demand to integrate more devices within limited space continues to grow. To overcome these constraints, “vertically stacked transistors,” in which current-carrying channels are vertically layered, have emerged as a promising alternative for next-generation 3D semiconductors. However, conventional vertically stacked transistors suffer from a critical drawback in which gate electric signals are not delivered uniformly into the channel interior due to their electrode structure, consequently leading to current leakage or unstable device operation as the channel length becomes shorter.
□ To address this issue, the research team proposed a “dual-modulation structure” in which two gates—positioned above and below—control the channel through different mechanisms. This represents an innovative approach in which current flows in a sandwich-like configuration, with the upper and lower electrodes facing each other across the channel.
□ The research team created microscopic openings in the lower electrode to allow electric signals to penetrate deeper into the channel interior, and adopted an upper electrode made of the novel material “graphene” to enable more precise control of current flow. In addition, a blocking layer was incorporated in regions prone to current leakage, fundamentally eliminating pathways that could cause unnecessary power loss.
□ As a result, the research team realized a current conduction layer in an extremely thin planar form at the nanometer scale, far thinner than the diameter of a human hair. The device suppresses the minute leakage current that flows when the power is off to an extremely low level of 10 -12 A (amperes), while demonstrating excellent performance in clearly distinguishing between the on and off states. The device also delivers sufficient output current even at low voltages and maintains stable operation even under harsh conditions such as light exposure or prolonged operation.
□ This technology does not require costly ultra-precise alignment processes or high temperatures, thereby making it highly advantageous for scaling to large-area or multilayer stacked structures. The technology is expected to bring significant advances across a wide range of industrial fields, such as highly integrated 3D semiconductors, next-generation low-power logic devices, memory technologies, and flexible electronics.
□ “This research presents a new dual-gate design strategy that enables stable operation even in nanoscale channels,” stated Professor Jae Eun Jang of the Department of Electrical Engineering and Computer Science at DGIST. “By overcoming the fundamental limitations of conventional vertical transistors, the technology is expected to serve as an important solution for accelerating the era of next-generation low-power, highly integrated 3D semiconductors.”
□ Meanwhile, the research was supported by the InnoCORE Program of the Ministry of Science and ICT and the National Research Foundation of Korea, and the findings were published online in Advanced Science , a leading international journal in the field.
Advanced Science
Dual-Modulated Vertically Stacked Transistors with Fully Laminated Plate-Type Architecture Featuring Nanoscale Channel Length