Add BrightSurf on Google Email

Wafer-scale growth of ultrathin amorphous tellurium oxide via pulsed laser deposition for p-channel transistors

09.17.26 | Tsinghua University Press

Oxide semiconductors have become a cornerstone of transparent electronics, chemical sensors, and next-generation integrated circuits. While n-type oxide semiconductors such as InGaZnO have achieved remarkable success, the lack of high-performance p-type counterparts has remained a major obstacle to realizing fully oxide-based complementary electronics.

Tellurium oxide (TeO x ) has recently emerged as one of the most promising p-type oxide semiconductors because of its relatively high hole mobility, tunable band structure, and compatibility with van der Waals electronic systems. However, existing fabrication methods generally rely on complex growth processes, localized synthesis, or relatively high processing temperatures, making wafer-scale manufacturing difficult.

Researchers from Shenzhen University and Nanning Normal University have now developed a scalable method to fabricate wafer-scale ultrathin amorphous TeO x thin films by combining pulsed laser deposition (PLD) with low-temperature thermal oxidation.

The study has been published in Nano Research on July 7, 2026

"Developing scalable p-type oxide semiconductors has become one of the key challenges for future oxide electronics," said the corresponding author. "Our approach combines the precise thickness control of pulsed laser deposition with a low-temperature oxidation process, enabling wafer-scale amorphous TeOx films with controllable composition and electronic properties."

The researchers deposited ultrathin Te films using PLD and subsequently oxidized them at approximately 180 °C. By simply adjusting the annealing time, they continuously tuned the Te/O stoichiometric ratio from 0.34 to 1.49 and increased the optical bandgap from 0.59 to 0.98 eV. This controllable oxidation process provides an effective route for engineering the electronic structure of TeOx.

The resulting p-channel thin-film transistors exhibited excellent electrical performance, including a room-temperature hole mobility of 47.6 ± 2 cm 2 ·V -1 ·s -1 , which remained 41.8 ± 0.5 cm 2 ·V -1 ·s -1 at 80 K. The current on/off ratio increased from approximately 2 × 10³ at room temperature to 1.3 × 10⁷ at low temperature. The devices also demonstrated excellent uniformity and reproducibility across the wafer.

Compared with previously reported TeO x transistors, the present strategy combines wafer-scale fabrication, ultrathin amorphous films, low-temperature processing, and competitive device performance within a simple and scalable manufacturing process.

"Our work demonstrates that amorphous oxide semiconductors can simultaneously achieve large-area manufacturability and excellent transistor performance," the authors said. "We believe this strategy will accelerate the development of p-type oxide electronics and promote future applications in complementary oxide integrated circuits, flexible electronics, and transparent electronic systems."

Future work will focus on integrating the TeO x platform with high-performance n-type oxide semiconductors to realize fully oxide-based CMOS circuits and large-area electronic systems.

This work was supported by the National Natural Science Foundation of China (Grant Nos. 42467063 and 62404137), Shenzhen Science and Technology Program (Grant Nos. JCYJ20250604182650067, JCYJ20240813142715021, JCYJ20220531103411026, JCYJ20241202124510014, and ZDSYS201707271014468), Shenzhen Strategic Emerging Industry Support Plan (Grant NO. F-2023-Z99-509043), Guangxi Natural Science Foundation (2025JJA150150), College Young and Middle-aged Teachers’ Basic Ability Improvement Project of Guangxi, China (No. 2024KY0402), and Guangxi Youth Talents Program. The authors thank Dr. Zhongyang Liu from the Photonics Center of Shenzhen University and Dr. Nan Jian from the Electron Microscope Center of Shenzhen University for their technique supports.

DOI Link:

https://doi.org/10.26599/NR.2026.94909005

About Nano Research

Nano Research is a peer-reviewed, open access, international and interdisciplinary research journal, sponsored by Tsinghua University and the Chinese Chemical Society, published by Tsinghua University Press on the platform SciOpen. It publishes original high-quality research and significant review articles on all aspects of nanoscience and nanotechnology, ranging from basic aspects of the science of nanoscale materials to practical applications of such materials. After 18 years of development, it has become one of the most influential academic journals in the nano field. Nano Research has published more than 1,000 papers every year from 2022, with its cumulative count surpassing 8,000 articles. In 2025 InCites Journal Citation Reports, its 2025 IF is 9.4 (8.3, 5 years), and it continues to be the Q1 area among the four subject classifications. Nano Research Award, established by Nano Research together with TUP and Springer Nature in 2013, and Nano Research Young Innovators (NR45) Awards, established by Nano Research in 2018, have become international academic awards with global influence.

Nano Research

10.26599/NR.2026.94909005

Wafer-Scale Growth of Ultrathin Amorphous Tellurium Oxide via Pulsed Laser Deposition for p-Channel Transistors

7-Jul-2026

Keywords

Article Information

Contact Information

Mengdi Li
Tsinghua University Press
limd@tup.tsinghua.edu.cn

How to Cite This Article

APA:
Tsinghua University Press. (2026, September 17). Wafer-scale growth of ultrathin amorphous tellurium oxide via pulsed laser deposition for p-channel transistors. Brightsurf News. https://www.brightsurf.com/news/1ZZPK951/wafer-scale-growth-of-ultrathin-amorphous-tellurium-oxide-via-pulsed-laser-deposition-for-p-channel-transistors.html
MLA:
"Wafer-scale growth of ultrathin amorphous tellurium oxide via pulsed laser deposition for p-channel transistors." Brightsurf News, Sep. 17 2026, https://www.brightsurf.com/news/1ZZPK951/wafer-scale-growth-of-ultrathin-amorphous-tellurium-oxide-via-pulsed-laser-deposition-for-p-channel-transistors.html.