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Machine learning co-optimizes flexible carbon nanotube transistors for low-voltage logic

09.17.26 | Tsinghua University Press

Flexible electronics could underpin next-generation wearable sensors, smart healthcare systems and Internet of Things devices. Carbon nanotube thin-film transistors (CNT-TFTs) are a strong candidate for these applications because they combine high carrier mobility, low-temperature processability and mechanical compliance. Yet reliable low-voltage logic on flexible substrates remains difficult: drive current, threshold voltage, zero-bias leakage, subthreshold swing and on/off ratio must all be balanced, and each is affected by multiple, tightly coupled fabrication steps.

A team led by Youfan Hu at the Center for Carbon-based Electronics and the School of Electronics, Peking University, has developed a machine-learning-guided process co-optimization framework that maps circuit-level requirements onto fabrication strategies. Using low-voltage digital logic as a test case, the researchers demonstrated 2 V circuits on flexible substrates, including a ring oscillator, a complete set of basic logic gates and a 1-bit full adder. The study was published in Nano Research on July 7, 2026.

According to Hu, corresponding author and professor at Peking University, the key is to optimize for the target circuit rather than maximize any single transistor metric. Machine learning is well suited to the task because it can identify empirical relationships between descriptors of a multistep process and multidimensional electrical responses in experimental data.

To build the model, the team created a library of 80 multistep fabrication recipes and measured more than 800 devices. They trained a decision-tree-based random forest using a weighted evaluation score that combined five circuit-relevant metrics; field-effect mobility received the largest weight, 40%, as a proxy for drive current and switching speed. The model achieved a coefficient of determination (R²) of 0.91. Feature-importance analysis identified encapsulation and post-fabrication annealing as the most influential steps in the studied process flow.

Guided by the model, the researchers used grid search to co-optimize the full fabrication flow. The resulting enhancement-mode CNT-TFTs on flexible polyimide achieved extracted field-effect mobilities of up to 71 cm² V⁻¹ s⁻¹, width-normalized zero-bias leakage current as low as 0.2 pA μm⁻¹ and on/off current ratios of 10⁶.

Inverters, which are highly sensitive to device balance, provided a stringent unit-level test. Compared with conventional geometric-ratio tuning, process optimization placed the switching threshold near VDD/2 without increasing device area, raised voltage gain from about 15 to 60, reduced high-level output loss from about 0.2 V to 0.03 V, improved the two noise margins from 20% and 32% to 36% and 42%, and cut static power consumption by roughly a factor of eight.

The same platform supported a five-stage ring oscillator operating at 60 kHz, a complete set of near-rail-to-rail basic logic gates (NOT, NAND, NOR, AND, OR and XOR), and a 1-bit full adder built from 11 NAND gates. Together, these results demonstrate reliable dynamic and cascaded logic at low supply voltage on a flexible substrate.

The work establishes a practical process-to-circuit route for refining CNT-TFT fabrication and provides a framework for application-specific development of flexible integrated electronics. The approach could also be adapted to other emerging thin-film technologies.

Next, the team plans to extend the data-driven framework to larger-scale circuit integration and other thin-film material systems, with potential applications in wearable sensors, flexible displays and smart healthcare devices.

Other contributors are Qibei Gong, Fan Xia and Lanyue Gan of Peking University, and Li Xiang of Hunan University in Changsha, China.

This work was supported by the National Key R&D Program of China (Grant No. 2022YFB4401603).

DOI Link:

https://doi.org/10.26599/NR.2026.94909009

About Nano Research

Nano Research is a peer-reviewed, open access, international and interdisciplinary research journal, sponsored by Tsinghua University and the Chinese Chemical Society, published by Tsinghua University Press on the platform SciOpen. It publishes original high-quality research and significant review articles on all aspects of nanoscience and nanotechnology, ranging from basic aspects of the science of nanoscale materials to practical applications of such materials. After 18 years of development, it has become one of the most influential academic journals in the nano field. Nano Research has published more than 1,000 papers every year from 2022, with its cumulative count surpassing 8,000 articles. In 2025 InCites Journal Citation Reports, its 2025 IF is 9.4 (8.3, 5 years), and it continues to be the Q1 area among the four subject classifications. Nano Research Award, established by Nano Research together with TUP and Springer Nature in 2013, and Nano Research Young Innovators (NR45) Awards, established by Nano Research in 2018, have become international academic awards with global influence.

Nano Research

10.26599/NR.2026.94909009

Machine learning co-optimizes flexible carbon nanotube transistors for low-voltage logic

7-Jul-2026

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Mengdi Li
Tsinghua University Press
limd@tup.tsinghua.edu.cn

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APA:
Tsinghua University Press. (2026, September 17). Machine learning co-optimizes flexible carbon nanotube transistors for low-voltage logic. Brightsurf News. https://www.brightsurf.com/news/80E0VPQ8/machine-learning-co-optimizes-flexible-carbon-nanotube-transistors-for-low-voltage-logic.html
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"Machine learning co-optimizes flexible carbon nanotube transistors for low-voltage logic." Brightsurf News, Sep. 17 2026, https://www.brightsurf.com/news/80E0VPQ8/machine-learning-co-optimizes-flexible-carbon-nanotube-transistors-for-low-voltage-logic.html.