Dipole‑driven charge trapping in monolayer janus mosse for ultrathin nonvolatile memory devices

As the demand for high-speed, energy-efficient memory technologies continues to grow, the limitations of conventional flash memory in terms of operation speed, data retention, and scalability become more pronounced. Now, researchers from the School of Materials Science and Engineering at Kumoh National Institute of Technology, Chungnam National University, and Gwangju Institute of Science and Technology, led by Professor Min Sup Choi and Professor Hyun Ho Kim, have presented a breakthrough 2D flash memory device employing monolayer Janus MoSSe as the charge-trapping layer. This work offers valuable insights into the development of next-generation nonvolatile memories with unprecedented performance metrics.

Why Janus MoSSe Memory Matters

· Ultrafast Charge Trapping: Janus MoSSe-based floating-gate memory exhibits charge-trapping rates up to 8.96×10 ¹⁴ cm ^-2 s ^-1 , enabling high-speed program/erase operations.

· Superior Retention: The intrinsic out-of-plane dipole moment in Janus MoSSe provides deeper trapping states and enhanced charge confinement, achieving stable data retention exceeding 10 ⁸ seconds.

· Energy Efficiency: The built-in dipole field enables efficient charge trapping even with ultrathin h-BN tunneling layers (down to 6 nm), reducing operating voltages while maintaining large memory windows.

· Neuromorphic Applications: The devices demonstrate synaptic plasticity including paired-pulse facilitation and long-term potentiation/depression, enabling artificial neural network simulations with 94.27% recognition accuracy.

Innovative Design and Features

· Janus Material Structure: The unique asymmetric configuration of Janus MoSSe, with sulfur atoms on one side and selenium on the other, creates a permanent vertical dipole moment unavailable in conventional symmetric 2D materials.

· All-van der Waals Heterostructure: The device architecture integrates multilayer graphene (MLG)/MoS ₂ /h-BN/Janus MoSSe in a vertically stacked configuration, ensuring atomically clean interfaces and precise electrostatic control.

· Optimized Tunneling Barrier: Systematic investigation of h-BN thickness (4–16 nm) reveals that the optimal 6 nm thickness achieves the largest memory window (ΔV/VG,max of 70%), enabled by dipole-assisted charge injection and retention.

· Theoretical Validation: Density functional theory calculations confirm that injected electrons localize at selenium sites due to strong charge-dipole interactions, providing fundamental understanding of the enhanced trapping mechanism.

Applications and Future Outlook

· High-Density Data Storage: The demonstrated memory window of ~80 V at 10 nm h-BN and record-breaking performance at 6 nm thickness positions this technology for next-generation ultrathin, flexible nonvolatile memories.

· In-Memory Computing: The multi-level storage capability and analog synaptic characteristics enable implementation of artificial neural networks, convolutional neural networks, and advanced neuromorphic computing systems.

· Scalable Manufacturing: The fabrication approach is compatible with wafer-scale single-crystal growth methods and room-temperature plasma substitution techniques, ensuring practical scalability for industrial applications.

· Challenges and Opportunities: The review highlights the current limitations in large-area Janus MoSSe synthesis due to manual fabrication processes. Future research will focus on developing automated transfer techniques and exploring alternative tunneling dielectrics such as ALD-deposited Al ₂ O ₃ and HfO ₂ to fully realize the commercial potential of Janus TMD-based memory devices.

This comprehensive study establishes a new design paradigm for 2D flash memory devices by leveraging the asymmetric dipolar nature of Janus MoSSe, achieving unprecedented memory performance metrics in a simple and scalable architecture. It highlights the importance of interdisciplinary research in materials science, condensed matter physics, and device engineering to drive innovation in this field. Stay tuned for more groundbreaking work from Professor Min Sup Choi and Professor Hyun Ho Kim at Chungnam National University and Gwangju Institute of Science and Technology!

Nano-Micro Letters

10.1007/s40820-026-02078-y

News article

Dipole‑Driven Charge Trapping in Monolayer Janus MoSSe for Ultrathin Nonvolatile Memory Devices

26-Jan-2026