A research team led by Professor Taesung Kim from the School of Mechanical Engineering at Sungkyunkwan University has developed hafnium oxide-based ferroelectric transistor arrays and successfully demonstrated their application in next-generation artificial intelligence (AI) hardware.
With the rapid expansion of artificial intelligence (AI) and Internet of Things (IoT) technologies, there is a growing demand for new computing architectures capable of processing large volumes of data at high speed while minimizing power consumption. However, most conventional computing systems adopt the von Neumann architecture, in which memory and processing units are physically separated. This structural separation results in data transfer bottlenecks, leading to latency and high energy consumption. As an alternative to overcome these limitations, in-memory computing—where computations are performed directly within memory devices—has emerged as a key enabling technology for next-generation AI hardware.
The research team implemented a novel ferroelectric transistor structure using hafnium–zirconium oxide (HfZrO₂), a material highly compatible with conventional semiconductor fabrication processes. This material can maintain electric polarization even at nanometer-scale thickness and can be directly integrated into existing CMOS processes. Using atomic layer deposition (ALD), the team precisely and repeatedly stacked HfO₂ and ZrO₂ at the atomic level to synthesize ultrathin HfZrO₂ films. Subsequently, rapid thermal annealing (RTA) below 400°C was employed to reliably induce ferroelectric properties.
The core of this study lies in a design strategy known as “lattice engineering.” Inside a material, atoms are arranged in a regular lattice structure, and the physical properties—particularly ferroelectricity—are determined by this atomic arrangement. Instead of modifying the chemical composition or introducing additional elements, the researchers controlled the atomic arrangement by utilizing microscopic stress generated during thermal processing. By placing the ferroelectric thin film between metal electrodes with different thermal expansion coefficients, tensile stress was generated during annealing. This stress reorganized the atomic structure within HfZrO₂ and selectively stabilized the orthorhombic phase, which is responsible for ferroelectric behavior. This approach demonstrates a new method of precisely controlling material properties through externally engineered mechanical stress without altering the material’s chemical composition.
As a result, devices incorporating tungsten (W) electrodes achieved a wide memory window of approximately 11 V and an on/off current ratio exceeding 10⁶. The devices also maintained stable operation over more than 10¹² switching cycles under 80 ns pulse conditions. Furthermore, uniform switching voltage distributions were observed across arrays consisting of 350 devices, experimentally confirming scalability for large-area integration. Each device exhibited up to 22 distinct conductance states, with a conductance ratio (Gmax/Gmin) of approximately 160, providing a sufficient dynamic range for analog weight representation. Long-term potentiation (LTP) and long-term depression (LTD) characteristics were also stably demonstrated, successfully emulating synaptic learning behavior.
Notably, this study distinguishes itself by numerically demonstrating that device operation modes can be controlled solely through electrode engineering while maintaining the same HfZrO₂ film stack. In symmetric W/HZO/W structures, ferroelectricity was maximized, resulting in nonvolatile memory operation, whereas other electrode combinations exhibited volatile or semi-volatile behavior. This reconfigurable structure enables selective implementation of logic and memory functions within a single process platform.
By incorporating experimentally measured device characteristics into a convolutional neural network (CNN) simulation based on VGG-8, the team achieved an image classification accuracy of 97.2% on the CIFAR-10 dataset. This result confirms that high AI inference performance can be maintained even when accounting for practical device nonidealities such as nonlinearity, weight asymmetry, and device-to-device variations.
Additionally, a 9×2 ferroelectric transistor array was utilized to directly implement edge detection and image filtering operations in the analog domain, experimentally verifying the feasibility of in-memory multiply–accumulate (MAC) operations.
Professor Taesung Kim stated, “This study is significant in that we precisely controlled the ferroelectric phase through stress-driven lattice engineering without altering the chemical composition.” He added, “By simultaneously achieving high endurance and precise analog weight control, we have presented a practical platform expandable to low-power edge AI and neuromorphic semiconductor applications. This work provides a technological foundation for the physical integration of memory and computation and marks an important milestone in the development of next-generation in-memory computing technologies.”
This research was published online on January 27 in ACS Nano (Impact Factor 16.1, JCR top 5% in the field of nanoscience).
※ Title: Thermal Expansion-Engineered Ferroelectric Transistor Arrays for Scalable Edge AI Computing
※ Journal: ACS Nano
※ DOI: https://pubs.acs.org/doi/10.1021/acsnano.5c14095
※ PURE: https://pure.skku.edu/en/persons/taesung-kim/
※ Authors:
-Corresponding author: Prof. Taesung Kim
-First author: Geonwook Kim (integrated M.S./Ph.D. program); Hyunho Seok (Postdoctoral Researcher); Sihoon Son (integrated M.S./Ph.D. program); Hyunbin Choi (Ph.D. candidate).
ACS Nano
Thermal Expansion-Engineered Ferroelectric Transistor Arrays for Scalable Edge AI Computing