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NUS CDE researchers design AI hardware that filters out irrelevant visual data

09.25.26 | National University of Singapore College of Design and Engineering

When we read a car’s number plate, we tend to focus only on the numbers and letters, paying little attention to the surrounding buildings or sky. An artificial-intelligence (AI) system, however, may still process those surrounding details, consuming energy even when they contribute little to the task. As cameras capture ever more detailed images, this unnecessary processing wastes more energy — a growing problem for electronics with limited power, such as battery-powered security cameras, drones and various edge devices.

Researchers at the College of Design and Engineering, National University of Singapore (NUS CDE), have developed a reconfigurable transistor that can switch between filtering image data and performing functions within an AI network. Using this device, they designed a system that passes only selected image regions to the network for analysis. In a handwritten-digit recognition simulation, it required about a third fewer active hardware blocks with almost no loss of accuracy.

Findings from the study, led by Professor Ang Kah-Wee from the Department of Electrical and Computer Engineering at NUS CDE, were published in Nature Electronics on 14 September 2026.

“Our approach could make it easier to run several visual tasks on devices with limited power,” said Prof Ang. “The hardware can allocate its resources according to what each task needs, giving us more flexibility to balance recognition accuracy against energy consumption.”

Thou shalt not pass

The team’s design uses a spiking neural network, a form of AI inspired by how nerve cells communicate. The network’s artificial neurons gather incoming signals and fire brief pulses, or spikes, when enough input has accumulated. Typically, image details that do not help with recognition can still trigger this activity and consume power.

To reduce this unnecessary activity, the team placed rule-based circuits, known as logic circuits, before the neural network. Control signals specify which image regions to keep, and the circuits pass on those pixels while blocking the rest. Only the selected data are then converted into spikes for the network to process. The researchers call this arrangement a “spiking neural network-in-logic” architecture. “The idea is analogous to selective attention: first identify the information relevant to the task, discard what is unnecessary, and only then engage the neural network,” added Prof Ang.

In this design, the team’s reconfigurable transistors provide the building blocks for both the filtering circuits and the neural networks. They are grouped into small units called tiles, which can be assigned to either filtering or network calculations as needed. When filtering removes unnecessary image data, fewer tiles are engaged in the network, reducing the amount of hardware required to process the image.

Role-shifting transistors

Allowing tiles to switch roles depends on the behaviour of their transistors. Filtering requires reliable switching, while neural-network functions require both temporary responses and stored information, both of which usually rely on disparate device structures. The researchers designed the material layers and electrical controls together to provide all these behaviours in one single transistor.

The device carries current through an atom-thin layer of molybdenum disulfide, a two-dimensional semiconductor. Its thinness allows two control electrodes, called gates, to precisely regulate the current. One gate incorporates hafnium zirconium oxide, a ferroelectric material in which voltage can switch the alignment of positive and negative charges. This layer helps the device produce either a temporary or a lasting response to an electrical signal.

The team controls these responses by changing the duration of voltage pulses applied to that gate. Brief pulses produce responses that build up and then fade away, allowing the device to mimic a neuron. Meanwhile, longer pulses trap electrical charge, leaving a lasting change in how easily current flows. This change stores a synaptic weight, allowing the device to represent the strength of a connection between neurons. Under steady voltages, the same device can perform logic operations to filter data.

“We fabricated the transistors using processes compatible with mainstream chip manufacturing. Importantly, the atomically thin MoS₂ semiconductor layer, grown by metal-organic chemical vapor deposition (MOCVD) in our lab, exhibits high quality and excellent uniformity across the wafer,” said Professor Lance Li from the Department of Materials Science and Engineering at NUS CDE, a co-author of the new paper. “This combination of material quality and wafer-scale uniformity is critical for ensuring that large numbers of devices perform consistently, which is essential for practical AI hardware and other large-scale integrated applications.”

“One big challenge was to preserve reliable switching for logic while making the same device retain some signals and let others fade,” added Prof Ang. “We worked closely with Prof Li and his team from the Department of Materials Science and Engineering to understand what happens where the layers meet, then used that understanding to design the transistor and the electrical signals that control it.”

Adapting to different tasks

To test whether the network could recognise images with fewer active tiles, the researchers ran simulations based on measurements of their transistors. They first compared recognition of handwritten digits using full 28x28-pixel images with versions cropped to 20x20 pixels.

Cropping reduced the total number of active tiles by about 36 per cent, even after including those needed for filtering. The number of synaptic weights stored in the network fell by almost half. Importantly, recognition accuracy declined by only 0.3 per cent from the full-image baseline of 95.9 per cent.

Cropping even more tightly began to remove useful information. For example, at 16x16 pixels, parts of the digits were cut away, and accuracy dropped to 94.4 per cent. The useful amount of filtering, therefore, depends on which visual features a task needs.

To assess the potential energy savings across different tasks, the team also modelled a traffic scene. Recognising a vehicle requires a wider view of its shape, while reading its number plate needs a smaller region with finer detail. Selecting the appropriate region changes how many tiles are needed for the task.

In a simulation using a 3,072-pixel traffic image, selecting the vehicle region reduced estimated energy consumption by about 59 per cent compared with processing the full image. Further selection of the smaller number-plate region reduced it even more, to about 77 per cent. The simulations indicated that the energy advantage grew as image resolution increased. These estimates cover the computing arrays and exclude supporting circuits.

Moving forward, the team plans to develop AI accelerator chiplets, small chips that work together to speed up AI computations. These would combine computing architectures that manage energy use with new memory technologies and high-speed connections that transfer data using light. Testing them on realistic AI workloads would allow the researchers to assess energy efficiency, latency and data movement across the system.

For vision tasks in particular, the ability to select relevant information could benefit autonomous vehicles, drones and smart cameras, which need to analyse large amounts of sensor data rapidly while keeping power consumption as low as possible.

“Ultimately, our goal is to increase computing performance without a corresponding increase in power consumption, with applications ranging from AI infrastructure to intelligent sensing and autonomous systems,” added Prof Ang. “This could be an important direction towards more adaptive and energy-efficient AI at the edge, where every computation, and every joule, matters.”

This research is supported by the Agency for Science, Technology and Research (A*STAR) under its RIE2025 Energy-aware Accelerated Computing (EAC) Programme (H25-MSR3439) and the Ministry of Education Singapore (MOET32024-0001).

Nature Electronics

10.1038/s41928-026-01706-0

Experimental study

Not applicable

A spiking neural network-in-logic architecture based on reconfigurable molybdenum disulfide dual-gate transistors with ferroelectric gating

14-Sep-2026

Keywords

Article Information

Contact Information

Zi Jing Wan
National University of Singapore College of Design and Engineering
zijing@nus.edu.sg
Charis Welikande
National University of Singapore College of Design and Engineering
welikande@nus.edu.sg
CDE News
National University of Singapore College of Design and Engineering
cdenews@nus.edu.sg

How to Cite This Article

APA:
National University of Singapore College of Design and Engineering. (2026, September 25). NUS CDE researchers design AI hardware that filters out irrelevant visual data. Brightsurf News. https://www.brightsurf.com/news/8X5R7GM1/nus-cde-researchers-design-ai-hardware-that-filters-out-irrelevant-visual-data.html
MLA:
"NUS CDE researchers design AI hardware that filters out irrelevant visual data." Brightsurf News, Sep. 25 2026, https://www.brightsurf.com/news/8X5R7GM1/nus-cde-researchers-design-ai-hardware-that-filters-out-irrelevant-visual-data.html.