Researchers have developed an innovative self-cleaning van der Waals lamination method for two-dimensional materials, offering a practical route toward cleaner interfaces, more reliable stacking, and higher-performance 2D electronic devices. Two-dimensional materials are regarded as promising building blocks for next-generation electronics because of their atomically thin nature, excellent electrical properties, and broad compatibility with heterogeneous integration. However, their performance is extremely sensitive to interface quality. During conventional transfer or lamination processes, molecular adsorbates, air, water, and other contaminants are often trapped between adjacent layers. These trapped impurities can lead to bubbles, wrinkles, local strain, charge traps, and interfacial disorder, which seriously degrade device performance, uniformity, and long-term reliability.
To overcome this long-standing challenge, the research team proposed an elastic bevel thermal lamination strategy based on a specially designed elastic bevel stamp. The stamp consists of a mechanically compliant support and an ultra-flat viscoelastic adhesive layer. During lamination, the elastic bevel structure enables gradual and conformal contact between the target materials, while the viscoelastic adhesive layer provides stable support and intimate contact over large areas. More importantly, the lamination is performed at an optimized temperature of 150 °C. This moderate heating step promotes the desorption of physically adsorbed molecules from the surfaces of 2D materials, while the controlled lamination force continuously drives residual adsorbates and trapped air away from the interface. In this way, the process does not merely avoid contamination passively, but actively removes interfacial impurities during stacking, giving rise to a self-cleaning lamination effect.
This elastic bevel thermal lamination method, referred to as EBTL, can produce clean, flat, and uniform van der Waals stacks over large areas. Compared with traditional transfer techniques, the method significantly reduces interfacial bubbles and wrinkles, while maintaining the structural integrity of fragile 2D layers. The clean interfaces obtained by EBTL are directly reflected in improved optical, structural, and electrical properties. The researchers demonstrated interface yields above 95%, indicating that high-quality interfaces can be achieved with excellent reproducibility. Such a high yield is particularly important for practical 2D electronics, where device arrays and integrated circuits require not only high individual device performance, but also uniformity across large numbers of devices.
The advantages of EBTL were further verified through various electronic devices. In 2D field-effect transistors, the clean semiconductor–dielectric interfaces led to greatly suppressed charge trapping and improved electrical stability. For example, the transistor hysteresis was reduced to approximately 10 mV, demonstrating the formation of a high-quality interface with minimal interfacial disorder. In addition, the method was used to fabricate 2D heterojunction diodes with fast photoresponse, achieving ultrafast response times of approximately 470 ns. These results show that the self-cleaning lamination process can improve not only the static electrical characteristics of 2D devices, but also their dynamic response and functional performance.
Another important feature of this method is its versatility. EBTL is compatible with a wide range of 2D material systems and stacking architectures. It can be applied to wafer-scale monolayer materials, twisted bilayers, superlattices, and complex multilayer van der Waals structures. The method is also suitable for integrating different functional building blocks, including 2D semiconductor channels, metallic electrodes, insulating dielectrics, and other layered materials. This flexibility makes it possible to construct fully van der Waals-integrated device structures without relying heavily on conventional microfabrication processes that may damage or contaminate 2D materials, such as high-energy metal evaporation or the direct growth of ultrathin dielectrics.
To further demonstrate scalability, the researchers fabricated a fully van der Waals-laminated 2D transistor array containing 2400 devices. The large-scale device array exhibited good uniformity and reliable electrical performance, highlighting the potential of EBTL for scalable manufacturing. This result is particularly meaningful because one of the major obstacles facing 2D electronics is the transition from individual high-performance devices to large-area, statistically reliable integrated systems. By enabling clean and uniform lamination over extended areas, EBTL provides a practical solution to this challenge.
Overall, the self-cleaning EBTL strategy addresses a central bottleneck in the fabrication of 2D material devices: the formation of clean and reliable van der Waals interfaces. By combining controlled elastic contact, thermal desorption, and active impurity expulsion, the method enables high-quality stacking of 2D materials and their functional components. Its compatibility with large-scale materials, complex heterostructures, and fully laminated device architectures makes it a promising platform for high-performance 2D electronics. Looking forward, this approach may also play an important role in monolithic three-dimensional integration, where multiple 2D device layers can be stacked in the vertical direction with low thermal budget, minimal contamination, and high interface quality.
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