As artificial intelligence (AI) models continue to scale rapidly, computing systems are shifting from single-chip performance enhancement toward collaborative multi-chip scaling. In this context, scale-up networks play a critical role in providing high-bandwidth, low-latency interconnects between computing chips. However, current scale-up networks are approaching bottlenecks in bandwidth, energy efficiency and latency for chip-to-chip data transmission. To address this challenge, the Peking University team developed an optoelectronic distributed computing system based on an on-chip all-optical supernode. At the hardware level, the team developed a 400 Gbps silicon photonic transceiver chip as a high-speed electro-optic interface, together with a non-blocking 16 x 16 optical switch chip for scalable chip-to-chip connection and switching. The system performs data routing directly at the physical layer and supports a total aggregate switching bandwidth of up to 6.4 Tbps.
A particularly important feature of the optical switch chip is its total loss of less than 5 dB, including coupling loss. This low-loss performance enables high-speed error-free transmission without external optical gain compensation. Multiple switching paths also maintained error-free performance, indicating that the on-chip all-optical supernode can provide stable data streams for distributed inference while avoiding the additional latency introduced by retransmission. In addition, the device maintains a flat response over a spectral range exceeding 100 nm, providing an important foundation for wavelength-division multiplexing, bandwidth scaling and future system expansion.
The team further deployed a five-layer convolutional neural network for image denoising by assigning successive layers to individual computing units, and configured the optical switch chip to form a pipelined parallel computing mode. After each layer completed its computation, the intermediate feature maps were directly transmitted through the all-optical network to the next processing node. This allowed the network to process continuous input data streams in parallel, helping to alleviate the memory-wall problem caused by repeated compute-memory transfers in conventional architectures. Compared with a selected GPU baseline performing the same task, the system achieved more than a hundred-fold increase in inference speed while using only about one-ninth of the computing resources.
This work demonstrates the potential of on-chip all-optical supernodes for large-scale distributed intelligent computing. Looking ahead, with further advances in co-packaged optics, high-speed silicon photonic transceivers and the I/O rates of AI computing chips, on-chip all-optical supernodes could become an important foundation for high-bandwidth, low-latency and energy-efficient intelligent computing systems.
The study, entitled “On-chip large-scale all-optical interconnect for ultra-low-latency deep neural network inference,” has been published in National Science Review (NSR). Peking University is the leading institution. Zihan Tao, Yan Zhou, Weizhen Yu and Huajin Chang are the co-first authors, and Dr. Haowen Shu and Prof. Xingjun Wang are the corresponding authors.
National Science Review
Experimental study