A new semiconductor integration platform developed at Institute of Science Tokyo combines advanced chip packaging with high-density interconnects and improved thermal management. This combination of three complementary technologies helps overcome the key challenges in building high-performance artificial intelligence (AI) hardware. By enabling more precise chip placement, faster communication, and efficient cooling, the technology paves the way for more powerful and energy-efficient AI accelerators and high-performance computing systems.
Artificial intelligence (AI) is rapidly transforming technologies, creating a growing demand for faster and more powerful computing systems. Meeting these demands requires semiconductor chips that can process massive amounts of data at high speed. Now, instead of relying on individual chips, manufacturers are focusing on advanced semiconductor packaging, which combines multiple chips into a single package to improve computing performance. However, fitting these chips closer together while ensuring efficient communication and cooling remains challenging.
In this context, a research team led by Specially Appointed Project Professor Norio Chujo from the WOW Alliance Heterogeneous and Functional Integration Research Unit, Institute of Integrated Research, Institute of Science Tokyo (Science Tokyo), Japan, together with Researcher Hideki Kitada and Specially Appointed Project Professor Takayuki Oba from the same institute, in collaboration with the WOW Alliance, developed three core technologies to enable BBCube™, a next-generation semiconductor integration platform for AI systems. Their innovation was presented at the 2026 IEEE 76 th Electronic Components and Technology Conference (ECTC) held in Florida, USA, from May 26 to 29, 2026, and the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits held in Hawaii, USA, from June 14 to 18, 2026.
“We developed three key technologies required for advanced 2.5D and 3D integration: our proprietary high-density chip-on-wafer technology, bumpless chip interconnection technology, and multiscale thermal analysis technology,” explains Chujo.
Additionally, the team developed a high-density chip interconnection architecture based on the BBCube TM process. In this process, via last through-silicon vias (TSVs)—tiny vertical electrical pathways formed after the chips are placed—connect the chips without using the metal bumps required in conventional packaging. This bumpless structure allows many more electrical connections to be placed within a limited area.
By combining these fine-pitch interconnections with the highly accurate chip placement described above, which reduces the chip-to-chip spacing to 10 µm, the analysis indicates the potential to provide up to 16 times greater aggregate signal bandwidth within the same interconnection area while maintaining signal quality comparable to that of conventional micro-bump-based designs.
“By placing chips closer together and connecting them without conventional bumps, we can greatly increase the amount of data transferred within a limited area without sacrificing signal quality,” notes Chujo.
Another major obstacle was the heat buildup in densely packed electronics. To tackle this, the researchers used simulations to demonstrate how their waffle wafer structure reduced thermal resistance by approximately 52%. They further developed a multiscale thermal analysis method capable of evaluating heat distribution across an entire chip at 1 μm resolution using 100 million analysis points, making it possible to accurately assess emerging semiconductor designs.
Together, these three technologies form a single efficient platform, advancing next-generation semiconductor systems. By addressing some of the most pressing challenges in AI hardware, BBCube™ holds the potential to accelerate the development of faster and more energy-efficient systems with compact packaging, efficient connectivity, and effective heat dissipation. As semiconductor devices continue to grow in complexity, further development of such technologies may support more compact chip architectures, helping power the future of AI accelerators and high-performance computing systems.
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About Institute of Science Tokyo (Science Tokyo)
Institute of Science Tokyo (Science Tokyo) was established on October 1, 2024, following the merger between Tokyo Medical and Dental University (TMDU) and Tokyo Institute of Technology (Tokyo Tech), with the mission of “Advancing science and human wellbeing to create value for and with society.”
10.1109/VLSITchnologyandCir65830.2026.11577472
Experimental study
Not applicable
High-Density Chiplet Integration using Face-Down COW Processes with Bumpless Interconnects for Heterogeneous 3D Systems
3-Jul-2026
The authors declare no conflicts of interest